The present invention is directed to memory devices and, more particularly, to the fabrication of dynamic random access memory (DRAM) structures in a substrate.
Semiconductor dynamic random access memory devices (DRAMs) typically include a memory cell array region formed of a plurality of memory cells arranged in rows and columns and include a plurality of bit lines as well as a plurality of word lines that intersect the bit lines. Each memory cell of the array is located at the intersection of a respective word line and a respective bit line and includes a capacitor for storing data and a transistor for switching, such as a planar or vertical MOS transistor. The word line is connected to the gate of the switching transistor, and the bit line is connected to the source or drain of the switching transistor. When the transistor of the memory cell is switched on by a signal on the word line, a data signal is transferred from the capacitor of the memory cell to the bit line connected to the memory cell or from the bit line connected to the memory cell to the capacitor of the memory cell.
When data stored in one of the memory cells is read onto one of the bit lines, for example, a potential difference is generated between the bit line of the respective memory cell and the bit line of another memory cell which form a bit line pair. A bit line sense amplifier located in a support region of the DRAM and connected to the bit line pair senses and amplifies the potential difference and transfers the data from the selected memory cells to a data line pair.
The storage capacitors of the DRAMs are typically formed in deep trenches etched into the substrate. A plurality of layers of conductive and insulating materials is deposited in the deep trenches to produce the storage capacitor. The transistors of the DRAM are generally planar devices that are formed in the substrate, or in a subsequently formed layer, and are located at the side of the storage capacitor. Alternatively, the transistors of the DRAM are disposed vertically, directly above the storage capacitor in the upper part of the trench, which conserves surface area as well as allows for the formation of smaller sized transistors, resulting in the more DRAM cells being placed on a single chip.
An advantage of DRAMs over other types of memory technology is their low cost because of the simplicity and scaling characteristics of the memory cell. Though the DRAM memory cell is based on simple concepts, the actual design and implementation of such cells typically requires a highly complex DRAM design and process technology.
Part of the complexity in the manufacturing process of a DRAM is the difficulty of providing practical and repeatable selective etch processes, such as when a material is to be removed from a region of the DRAM while the same or another material that is located atop another region of the DRAM is to be left relatively intact. An example of such a process step is the contact-to-bit line (CB) etching step in which a nitride liner material located atop the source and/or drain region is etched. At the same time that the nitride liner layer is etched, the nitride cap atop the word line stack above the gate region must remain relatively intact to prevent electrical shorts between the word line and the bit line. However, the nitride liner layer etches at a relatively slow rate, whereas the nitride cap atop the word line stack etches at a much faster rate so that a significant portion of the relatively thick nitride cap is removed at the same time that the relatively thin nitride liner layer is etched. It is therefore difficult to obtain repeatable etching conditions that remove the thin nitride liner layer without risking exposure of the word line stack caused by removal of the nitride cap.
It is therefore desirable to provide a DRAM structure and fabrication process that avoids these problems.